EE613: High-frequency analog circuit design (2025)

This course focuses on the design of single and multi-stage opamps, focusing on non-idealities like noise, mismatch, non-linearity, an analog designer encounters in practice. Instructor: R. S. Ashwin Kumar (https://home.iitk.ac.in/~ashwinrs/) Course contents can be found at: https://home.iitk.ac.in…

69 videos · SSCD IIT Kanpur

• Cadence demo: Systematic design of a two-stage Miller OTA & tackling the gate parasitic capacitance
• Lecture 37: To do post schematic: Good layout practices & handling package parasitics
• Lecture 36: Intro to Low drop-out regulators (LDO); Understanding LDO as a 2-stage OTA in feedback
• Lecture 35(2): Self-biased bandgap reference
• Lecture 35(1): Fractional band-gap reference
• Lecture 34: Bandgap reference
• Lecture 33(2): Method of non-linear currents for estimating weak non-linearities
• Lecture 33(1): Using negative feedback to combat non-linearity
• Lecture 32: Non-linearity in fully-differential ckts; Techniques to realize a linear transconductor
• Lecture 31: Noise in fully differential circuits; Scaling analog circuits for noise and bandwidth
• Lecture 30: Input referred noise & offset in 5-transistor OTA and cascodes
• Lecture 29: Input referred noise voltage & current: Example calculations
• Lecture 28: Intro to noise; Input referred noise voltage and current
• Lecture 27(2): Common-mode to differential-mode conversion in diff amp & offset due to mismatch
• Lecture 27(1): Mismatch in current mirror
• Lecture 26(2): Random mismatch & process variations; Relative mismatch; Pelgrom's model
• Lecture 26(1): Fully differential two stage feedforward compensated OTA with current reuse
• Lecture 25: Common-mode rejection by CMFB & output impedance due to CMFB
• Lecture 24(2): Fully differential two-stage Miller compensated OTA with CMFB design considerations
• Lecture 24(1): CMFB variants (contd.)
• Lecture 23: Common-mode feedback variants
• Lecture 22(2): Need for common-mode feedback in fully differential opamps
• Lecture 22(1): Power supply rejection ratio of 5-transistor OTA; Need for differential signaling
• Lecture 21(2): Nested Miller & Feedforward compensation
• Lecture 21(1): So far in this course... A 26 minute recap
• Lecture 20(2): Feedforward compensation; comparison with Miller compensation
• Lecture 20(1): Ahuja compensation (contd.): Circuit implementation
• Lecture 19(2): Ahuja compensation: Pole locations; Intuition for complex poles in Ahuja compensation
• Lecture 19(1): Miller compensation: Adding a series resistor to eliminate RHP zero
• Lecture 18: Miller OTA: Circuit implementation; Need for DC negative feedback; Systematic offset
• Lecture 17(2): Rough design example of the two-stage Miller compensated OTA
• Lecture 17(1): Introducing the two-stage Miller compensated OTA
• Lecture 16(3): Understanding Miller & feed-forward compensation from root-locus
• Lecture 16(2): Time-domain perspective on why LHP zeros are good & RHP zeros are bad for stability
• Lecture 16(1): Time-domain understanding on why more poles makes the closed-loop system unstable?
• Lecture 15: Deriving phase margin from root locus; Loop gain more than one & 180deg phase: stable?
• Lecture 14(3): Need for multi-stage OTAs; 1st order systems in negative feedback
• Lecture 14(2): Poles & zeros in telescopic cascode
• Lecture 14(1): Detecting uncoupled poles; Summary on when to write pole as conductance by cap.
• Lecture 13(4): Poles and zeros in cascode
• Lecture 13(3): 5-transistor OTA: Summary of poles & zeros in differential mode
• Lecture 13(2): Zeros in differential mode in the five-transistor OTA (pole-zero cancellation)
• Lecture 13(1): Pole locations in the five-transistor OTA
• Lecture 12(5): Intuition for high-freq. pole. Why can't Miller effect be used for high-freq. pole?
• Lecture 12(4): Miller effect: Intuition behind low-frequency pole location in common-source config.
• Lecture 12(3): Poles & zeros in common-source configuration
• Lecture 12(2): Poles & zeros by inspection in common-drain configuration
• Lecture 12(1): Poles & zeros (recap); example of an uncontrollable and unobservable state
• Lecture 11(2): Test to find presence of zeros; Origin of zeros; Calculating zero location
• Lecture 11(1): Pole location; When can poles be approx as ratio of conductance & cap.?
• Lecture 10(2): Gain-boosted cascode; Gm boosting
• Lecture 10(1): Slew rate of a folded cascode OTA
• Lecture 9(1): Motivation for folded cascode opamp; Telescopic cascode opamp in unity feedback
• Lecture 9(2): Merits of folded-cascode: Input common-mode range, output range, unity feedback swings
• Lecture 8: Telescopic cascode: DC op. point, dc gain, input common-mode range & output swing limits
• Lecture 7: Systematic design of analog circuits using look-up tables (gm/Id based) & design example
• Lecture 6(3): Common mode & differential mode response of the 5-transistor OTA
• Lecture 6(2): Impedances at each node in the 5-transistor OTA
• Lecture 6(1): Example problems; Defining the impedance looking up and down into a node
• Lecture 5(2): Slew rate of the five-transistor OTA
• Lecture 5(1): Step response of a VCCS vs. VCVS in negative feedback with a capacitive load
• Lecture 4(3): Input common-mode range and output range calculations in the five-transistor OTA
• Lecture 4(2): Why input common-mode & output range are relevant in opamps?
• Lecture 4(1): Summary of differential amplifier; OTA vs opamp
• Lecture 3(3): The 5-transistor amplifier: Short-circuit transconductance & output resistance
• Lecture 3(2): The five-transistor amplifier: DC operating point
• Lecture 3(1): Differential amplifier: Differential mode & common-mode half circuits
• Lecture 2: Recap of Common source, drain & gate configurations; Re-intro to differential amplifier
• Lecture 1: MOSFET recap: Strong inversion vs. weak inversion vs. linear region; Universality of VCCS