COMPUTER ORGANIZATION AND ARCHITECTURE
Speaker : Ms. PRIYANKA KODURU
Curated by:
kmit vista (95 videos)
Currently Playing: TIMING & CONTROL
Speaker : Ms. PRIYANKA KODURU
Tracks in this Playlist
UNIT - 5_INTERPROCESSOR COMMUNICATION & SYNC
UNIT - 5_CACHE COHERENCE
UNIT - 5_INTERPROCESSOR ARBITRATION
UNIT - 5_INTERCONNECTION STRUCTURES
UNIT - 5_CHARACTERISTICS OF MULTIPROCESSORS
UNIT - 5_ARRAY PROCESSORS
UNIT - 5_BRANCH PREDICTION
UNIT - 5_DESIGN ISSUES: BRANCH HAZARDS
UNIT - 5_DESIGN ISSUES: RESOLVING DATA HAZARDS
UNIT - 5_DESIGN ISSUES: STRUCTURAL HAZARDS
UNIT - 5_RISC PIPELINE
UNIT - 5_DESIGN ISSUES: HAZARDS, DATA HAZARDS
UNIT - 5_EXAMPLE OF RISC & CISC, RISC VS CISC
UNIT - 5_RISC & CISC
UNIT - 5_VECTOR PROCESSING
UNIT - 5_ARITHMETIC PIPELINE
UNIT - 5_PIPELINING
UNIT - 5_INSTRUCTION PIPELINE
UNIT - 4_PARALLEL PROCESSING
UNIT - 4_ASSOCIATE MEMORY (OR) CONTENT ADDRESSABLE MEMORY PART-2
UNIT - 4_ INTERRUPT INITIATED IO
UNIT - 4_DIRECT MEMORY ACCESS
UNIT - 4_ASYNCHRONOUS DATA TRANSFER PART-1
UNIT - 4_ASYNCHRONOUS DATA TRANSFER PART-2
UNIT - 4_ASSOCIATE MEMORY PART -1
UNIT - 4_INPUT OUTPUT INTERFACE
UNIT - 4_MODES OF TRANSFER, PROGRAMMED IO
UNIT - 4_ASSOCIATE MASSOCIATE MEMORY (OR) CONTENT ADDRESSABLE MEMORY PART-1
UNIT - 4_CACHE MAPPING
UNIT - 4_CACHE MEMORY
UNIT - 4_AUXILIARY MEMORY
UNIT - 4_MAIN MEMORY PART - 2
UNIT - 4_MAIN MEMORY PART - 1
UNIT - 4_MEMORY HIERARCHY
UNIT - 3_DECIMAL ARITHMETIC OPERATIONS: BCD DIVISION
UNIT - 3_DECIMAL ARITHMETIC OPERATIONS: BCD MULTIPLICATION
UNIT - 3_BCD SUBTRACTION,DECIMAL ARITHMETIC OPERATIONS: BCD ADDITION & SUBTRACTION
UNIT - 3_BCD SUBTRACTION,DECIMAL ARITHMETIC OPERATIONS: BCD ADDITION & SUBTRACTION
UNIT - 3_BCD ADDITION PART 2
UNIT - 3_DECIMAL ARITHMETIC UNIT, BCD ADDITION PART-1
UNIT - 3_ FLOATING POINT DIVISION PART-2
UNIT - 3_FLOATING POINT DIVISION PART-1
UNIT - 3_FLOATING POINT MULTIPLICATION PART-2
UNIT - 3_FLOATING POINT MULTIPLICATION PART-1
UNIT - 3_FLOATING POINT ADDITION & SUBTRACTION PART-2
UNIT - 3_FLOATING POINT ADDITION & SUBTRACTION PART-1
UNIT - 3_MULTIPLICATION OF 2’S COMPLEMENT DATA (BOOTH’S ALGORITHM) PART-2
UNIT - 3_MULTIPLICATION OF 2’S COMPLEMENT DATA (BOOTH’S ALGORITHM) PART-1
UNIT - 3_ADDITION & SUBTRACTION OF 2’S COMPLEMENT DATA
UNIT - 3_SIGNED MAGNITUDE DIVISION PART-3
UNIT - 3_SIGNED MAGNITUDE DIVISION PART-2
UNIT - 3_SIGNED MAGNITUDE DIVISION PART-1
UNIT - 3_SIGNED MAGNITUDE MULTIPLICATION PART-2
UNIT - 3_SIGNED MAGNITUDE MULTIPLICATION PART-1
UNIT - 3_ADDITION AND SUBTRACTION OF SIGNED MAGNITUDE DATA PART-3
UNIT - 3_ADDITION AND SUBTRACTION OF SIGNED MAGNITUDE DATA PART-2
UNIT - 3_ADDITION AND SUBTRACTION OF SIGNED MAGNITUDE DATA PART-1
UNIT - 3_FLOATING POINT REPRESENTATION
UNIT - 3_COMPLEMENTS,FIXED POINT REP
UNIT - 3_BASICS, DATA TYPES
UNIT - 2_PROGRAM CONTROL INSTRUCTIONS
DESIGN OF CONTROL UNIT
MICROPROGRAM EXAMPLE PART-2
MICROPROGRAM EXAMPLE PART-1
ADDRESS SEQUENCING / MICROPROGRAM SEQUENCER
DATA MANIPULATION INSTRUCTIONS PART-2
DATA MANIPULATION INSTRUCTIONS PART-1
DATA TRANSFER INSTRUCTIONS
TYPES OF ADDRESSING MODES WITH EXAMPLE PART-2
ADDRESSING MODESTYPES OF ADDRESSING MODES WITH EXAMPLE PART-1
INSTRUCTION FORMATS PART 2
INSTRUCTION FORMATSTYPES OF INSTRUCTION FORMATS WITH EXAMPLE PART-1
GENERAL REGISTER ORGANIZATION
CONTROL MEMORY
INSTRUCTION CYCLE
MEMORY REFERENCE INSTRUCTIONS
TIMING & CONTROL
REGISTER REFERENCE INSTRUCTIONS
INTERRUPT CYCLE
INSTRUCTION CODES,INTRODUCTION TO COMPUTER INSTRUCTIONS
INPUT-OUTPUT INSTRUCTIONS
COMPUTER REGISTERS
COMMON BUS SYSTEMBUS AND MEMORY TRANSFER
DEFINITION OF COMPUTER ORGANIZATION,ARCHITECTURE
SHIFT MICROOPERATIONS
REGISTER TRANSFER,REGISTER TRANSFER LANGUAGE
LOGIC MICROOPERATIONS
INTRODUCTION TO MICROOPERATIONS,ARITHMATIC MICROOPERATIONS-1
INPUT-OUTPUT & INTERRUPTS
ARITHMETIC MICROOPERATIONS - Part - 2
INTRODUCTION, BLOCK DIAGRAM OF A DIGITAL COMPUTER
DEFINITION OF CO,DESIGN &CA
ARITHMETIC LOGIC SHIFT UNIT
DEFINITION OF COMPUTER ORGANIZATION,DESIGN & COMPUTER ARCHITECTURE
INTRODUCTION BLOCK DIAGRAM OF A DIGITAL COMPUTER